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1/63 preliminary data september 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. m58cr032c m58cr032d 32 mbit (2mb x 16, dual bank, burst ) 1.8v supply flash memory features summary n supply voltage v dd = 1.65v to 2v for program, erase and read v ddq = 1.65v to 3.3v for i/o buffers v pp = 12v for fast program (optional) n synchronous / asynchronous read burst mode read: 54mhz page mode read (4 words page) random access: 85, 100, 120 ns n programming time 10 m s by word typical double/quadruple word programming option n memory blocks dual bank memory array: 8/24 mbit parameter blocks (top or bottom location) n dual operations read in one bank while program or erase in other no delay between read and write operations n block locking all blocks locked at power up any combination of blocks can be locked wp for block lock-down n security 64 bit user programmable otp cells 64 bit unique device identifier one parameter block permanently lockable n common flash interface (cfi) n 100,000 program/erase cycles per block figure 1. packages n electronic signature manufacturer code: 20h top device code, m58cr032c: 88c8h bottom device code, m58cr032d: 88c9h fbga tfbga56 (zb) 6.5 x 10 mm
m58cr032c, m58cr032d 2/63 table of contents summary description . . . . . . . . ........................................... ........6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............................7 table 1. signal names . . . ........................................................7 figure 3. tfbga connections (top view through package). . . . . . . . . . . . . . . . ...............8 table 2. bank architecture . . . . . . . . . . . . . . . . . . . .....................................8 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . ..................................9 figure 5. security block and protection register memory map . . . . . . . . . . . . . ...............9 signal descriptions . . .........................................................10 address inputs (a0-a20). . . . . . . ..................................................10 data inputs/outputs (dq0-dq15). . . . . . . . . . . . . . ....................................10 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................10 output enable (g). . . . . . . . . . . . . . . . ..............................................10 write enable (w). . . . . . . . . . . . . ........................................... .......10 write protect (wp). . . . . . . . . . . . . . . . . . . ...........................................10 reset/power-down (rp). . . . . . . . . . . . . . ...........................................10 latch enable (l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................... ....10 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . ...........................................10 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................................10 v dd supply voltage (1.65v to 2v). . . . ..............................................10 v ddq supply voltage (1.65v to 3.3v). . . . ...........................................10 v pp program supply voltage (12v). . . ..............................................10 v ss and v ssq grounds. . . ................................. ......................11 bus operations. . . . . . . . . . . . . . ........................................... .......12 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................12 asynchronous page read. . . . . . ........................................... .......12 asynchronous write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output disable. . . ..............................................................12 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................12 reset/power-down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................12 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................12 synchronous single read. . . . . . . . . . . . . . . . . . . . ....................................12 synchronous burst read. . . . . . . . . . . . . . . . . . . . . ....................................13 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................13 figure 6. synchronous single read operation. . . . . . . . . . . . . . . . . . . . . . . . . . ..............14 burst configuration register . . . . . . . . . ...........................................15 read select bit (m15) . . . . . . . . . . . . . . . . ...........................................15 x-latency bits (m13-m11). . . . . . . . . . . . . . . . . . . . ....................................15 power-down bit (m10). . . . . . . . . ........................................... .......15 wait bit (m8).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................15 burst type bit (m7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................15 valid clock edge bit (m6).. . . . . . . . . . . . . . . . . . . . ....................................15
3/63 m58cr032c, m58cr032d wrap burst bit (m3) . . . ..........................................................15 burst length bits (m2-m0).. . . . . . . . . . ..............................................15 table 4. burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........17 figure 7. x-latency configuration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........18 figure 8. wait configuration sequence. . . . . . . ................................ .......18 command interface . . . . . . . . . . . . . . . . ...........................................19 read command. . . . . . . . . . . . . . ........................................... .......19 read status register command. . . . . . . . ...........................................19 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . .......................19 read cfi query command ......................... ..............................19 clear status register command. . . . . . . . ...........................................19 block erase command . . . . ......................................................19 bank erase command . . . . ......................................................20 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................20 double word program command . . . . . . . . . . . . . . ....................................20 quadruple word program command . . . . . . . . . . . ....................................21 program/erase suspend command . . . . . ...........................................21 program/erase resume command . . . . . ...........................................21 protection register program command . . . . . . . . .....................................22 block lock command . . . . . . . . . ........................................... .......22 block unlock command . . . . . . . . . . . . . . . . . . . . .....................................22 block lock-down command . . . ...................................................22 set burst configuration register command. . . . . . . . . . . . . . . . . . . . . . . . ..................22 table 6. commands . . . . . . . . . . ........................................... .......23 table 7. dual bank operations . . . . . . ..............................................24 table 8. read electronic signature. . . . . . . . . . . . .....................................24 table 9. read block protection . . ........................................... .......24 table 10. read protection register . . . . . . . . . . . . ....................................25 table 11. identifier codes . . . . . . ..................................................25 table 12. program, erase times and program, erase endurance cycles . . . . . ..............26 block locking .................................................................27 reading a block's lock status . . ..................................................27 locked state . . . . . . . . . . . . . . . . . . . . ..............................................27 unlocked state . . . . . . . . . .......................................................27 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 locking operations during erase suspend . . . ................................ .......27 block lock status . . . . . . . . . . . . . . . . . . . ...........................................28 lock status . . . . . . . . . . . . . . . . . . . . . ..............................................28 status register . . . . . . . . . . . . . ..................................................29 program/erase controller status (bit 7) . . . . . . . . .....................................29 erase suspend status (bit 6) . . . . . . . . . . ...........................................29 erase status (bit 5) . . . . . . .......................................................29
m58cr032c, m58cr032d 4/63 program status (bit 4) . . . . . . . . . . . . . ..............................................29 v pp status (bit 3). . . . . . . . . . . . . . . . . . . . ...........................................29 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 block protection status (bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........30 reserved (bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........30 table 15. status register bits . . . . . . . . . . . . . . . . . . ............................... ....30 maximum rating. . . . . . . . . . . . . . . . . . . . . ...........................................31 table 16. absolute maximum ratings. . . . . . . . . . . . . . . . . ..............................31 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........32 table 17. operating and ac measurement conditions. . . . . . . . . . . . ......................32 figure 9. ac measurement i/o waveform . . . . . . . ............................. .......32 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. capacitance. . . . . . . . . ........................................... .......32 table 19. dc characteristics - currents . . . . . . . . .....................................33 table 20. dc characteristics - voltages . . . . . . . . . ....................................34 figure 11. asynchronous read ac waveforms . . . ............................. .......35 figure 12. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....36 table 21. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ...........37 figure 13. synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . .......................38 table 22. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 14. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 23. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 15. write ac waveforms, chip enable controlled. . . . . . . . . . . . . . . . . . . . . ...........42 table 24. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . .......43 figure 16. reset and power-up ac waveforms . . . ............................. .......44 table 25. reset and power-up ac characteristics . . ...................................44 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, bottom view package outline. . 45 table 26. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, package mechanical data .....45 part numbering . . . . . . . . . ......................................................46 table 27. ordering information scheme . . . . . . ................................ .......46 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................47 table 28. document revision history . . . . . . . . . . .....................................47 appendix a. common flash interface . . . . . . ............................. .......48 table 29. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . .......................48 table 30. cfi query identification string . . . . . . . .....................................48 table 31. cfi query system interface information . ....................................49 table 32. device geometry definition. . . ............................................49 table 33. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5/63 m58cr032c, m58cr032d table 34. burst read information . . . . . . . . . . . . . .....................................51 table 35. security code area . . . . . . . . . . . . . . . . . ............................. .......52 appendix b. flowcharts and pseudo codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 18. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . ...........54 figure 20. quadruple word program flowchart and pseudo code . . ......................55 figure 21. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . ....56 figure 22. block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....57 figure 23. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . ...........58 figure 24. locking operations flowchart and pseudo code . . . . .........................59 figure 25. protection register program flowchart and pseudo code . . . . . . . . . . . ...........60 appendix c. command interface state tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 36. command interface states - lock table .....................................61 table 37. command interface states - modify table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....62
m58cr032c, m58cr032d 6/63 summary description the m58cr032 is a 32 mbit (2mbit x16) non-vola- tile flash memory that may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.65v to 2.0v v dd supply for the circuitry and a 1.65v to 3.3v v ddq supply for the input/output pins. an optional 12v v pp power supply is provided to speed up custom- er programming. the v pp pin can also be used as a control pin to provide absolute protection against program or erase. the device features an asymmetrical block archi- tecture. m58cr032 has an array of 71 blocks and is divided into two banks, banks a and b, provid- ing dual bank operations. while programming or erasing in bank a, read operations are possible in bank b or vice versa. only one bank at a time is allowed to be in program or erase mode. it is pos- sible to perform burst reads that cross bank boundaries. the bank architecture is summarized in table 2, and the memory maps are shown in figure 4. the parameter blocks are located at the top of the memory address space for the m58cr032c and at the bottom for the m58cr032d. each block can be erased separately. erase can be suspended, in order to perform either read or program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for page mode read. in synchronous burst mode, data is output on each clock cycle at frequencies of up to 54mhz. the m58cr032 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power up. the device includes a 128 bit protection register and a security block to increase the protection of a system's design. the protection register is di- vided into two 64 bit segments. the first segment contains a unique device number written by st, while the second one is one-time-programmable by the user. the user programmable segment can be permanently protected. the security block, pa- rameter block 0, can be permanently protected by the user. figure 5, shows the security block and protection register memory map. the memory is offered in a tfbga56, 0.75 mm ball pitch package and is supplied with all the bits erased (set to '1').
7/63 m58cr032c, m58cr032d figure 2. logic diagram table 1. signal names ai90067 21 a0-a20 w dq0-dq15 v dd m58cr032c m58cr032d e v ss 16 g rp wp v ddq v pp l k wait a0-a20 address inputs dq0-dq15 data input/outputs or address inputs, command inputs e chip enable g output enable w write enable rp reset/power-down wp write protect k burst clock l latch enable wait wait data in burst mode v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally
m58cr032c, m58cr032d 8/63 figure 3. tfbga connections (top view through package) table 2. bank architecture bank size parameter blocks main blocks bank a 8 mbit 8 blocks of 4 kword 15 blocks of 32 kword bank b 24 mbit - 48 blocks of 32 kword ai90001 dq1 dq13 dq3 dq12 dq6 dq8 d a1 a3 a6 a9 a12 a15 c a2 a5 a17 a18 a10 b a4 a7 a19 v pp a8 a11 a13 a 8 7 6 5 4 3 2 1 a20 g f e v ss v dd krp lw a14 wait a16 wp v ddq dq4 dq2 e a0 v ss dq15 dq14 dq11 dq10 dq9 dq0 g dq7 v ssq dq5 v dd v ddq v ssq nc nc
9/63 m58cr032c, m58cr032d figure 4. memory map figure 5. security block and protection register memory map ai90069 512 kbit or 32 kword 000000h 007fffh 512 kbit or 32 kword 1f0000h 1f7fffh top boot block address lines a20-a0 512 kbit or 32 kword 178000h 17ffffh total of 48 main blocks 512 kbit or 32 kword 180000h 187fffh 64 kbit or 4 kword 1ff000h 1fffffh 64 kbit or 4 kword 1f8000h 1f8fffh total of 15 main blocks total of 8 parameter blocks bank b bank a 64 kbit or 4 kword 000000h 000fffh 512 kbit or 32 kword 078000h 07ffffh bottom boot block address lines a20-a0 64 kbit or 4 kword 007000h 007fffh total of 8 parameter blocks 512 kbit or 32 kword 008000h 00ffffh 512 kbit or 32 kword 1f8000h 1fffffh 512 kbit or 32 kword 080000h 087fffh total of 15 main blocks total of 48 main blocks bank b bank a ai90004 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 88h 85h 84h 81h 80h security block protection register
m58cr032c, m58cr032d 10/63 signal descriptions see figure 2 logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a20). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. the address inputs for the memory array are latched on the rising edge of latch enable l. the address latch is transparent when l is at v il .in synchronous operations the address is also latched on the first rising/falling edge of k (de- pending on clock configuration) when l is low. during a write operation the address is latched on the rising edge of l or w, whichever occurs first. data inputs/outputs (dq0-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. both input data and commands are latched on the rising edge of write enable, w. when chip en- able, e, and output enable, g, are at v il the data bus outputs data from the memory array, the elec- tronic signature, manufacturer or device codes, the block protection status, the burst configura- tion register, the protection register or the status register. the data bus is high impedance when the chip is deselected, output enable, g, is at v ih , or reset/power-down, rp, is at v il . chip enable (e). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. when chip enable, e, is at v ih , the memory is deselected and the power consumption is reduced to the standby lev- el. chip enable can also be used to control writing to the command interface and to the memory ar- ray, while write enable, w, remains at v il . output enable (g). the output enable gates the outputs through the data buffers during a read op- eration. when output enable, g, is at v ih the out- puts are high impedance. write enable (w). the write enable controls the bus write operation of the memory's command interface. data are latched on the rising edge of write enable. write protect (wp). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the block cannot be changed. when write protect is at v ih , the lock-down is disabled and the block can be locked or unlocked. (refer to table 10, read pro- tection register). reset/power-down (rp). the reset/power- down input provides hardware reset of the memo- ry, and/or power-down functions, depending on the burst configuration register status. a reset or power-down of the memory is achieved by pulling rp to v il for at least t plph . when the reset pulse is given, the memory will recover from power- down (when enabled) in a minimum of t phel , t phll or t phwl (see table 25 and figure 16) after the rising edge of rp. after a reset or power-up the device is configured for asynchronous page read (m15=1) and the power save function is dis- abled (m10=0). all blocks are locked after a reset or power-down. either chip enable or write en- able must be tied to v ih during power-up to allow maximum security and the possibility to write a command on the first rising edge of write enable. latch enable (l). latch enable latches the ad- dress bits a0-a20 on its rising edge. the ad- dress latch is transparent when l is at v il and it is inhibited when l is at v ih . clock (k). the clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a k edge (rising or falling, according to the configuration set- tings) when l is at v il . k is don't care during asyn- chronous page mode read and in write operations. wait (wait). wait is an output signal used during burst mode read, indicating whether the data on the output bus are valid or a wait state must be in- serted. this output is high impedance when chip enable or output enable are at v ih or reset/pow- er-down is at v il . it can be configured to be active during the wait cycle or one clock cycle in ad- vance. v dd supply voltage (1.65v to 2v). v dd pro- vides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). it ranges from 1.65v to 2.0v. v ddq supply voltage (1.65v to 3.3v). v ddq provides the power supply to the i/o pins and en- ables all outputs to be powered independently from v dd .v ddq can be tied to v dd or it can use a separate supply. it can be powered either from 1.65v to 2.0v or from 1.65v to 3.3v. v pp program supply voltage (12v). v pp is a power supply pin. the supply voltage v dd and the program supply voltage v pp can be applied in any order. the pin can also be used as a control input. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low volt- age range (0v to 2v) v pp is seen as a control in- put. in this case a voltage lower than v pplk gives an absolute protection against program or erase,
11/63 m58cr032c, m58cr032d while v pp >v pp1 enables these functions (see ta- ble 19, dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on program or erase, however for double or quadruple word program the results are uncertain. if v pp is in the range 11.4v to 12.6v it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is com- pleted (see table 16 and 17). in read mode the current sunk is less then 0.5ma, while during pro- gram and erase operations the current may in- crease up to 10ma. v ss and v ssq grounds. v ss and v ssq grounds are the reference for the core supply and the input/ output voltage measurements respectively. note: each device in a system should have v dd ,v ddq and v pp decoupled with a 0.1 m f ca- pacitor close to the pin. see figure 10, ac mea- surement load circuit. the pcb trace widths should be sufficient to carry the required v pp program and erase currents.
m58cr032c, m58cr032d 12/63 bus operations there are two types of bus operations that control the device: asynchronous (read, page read, write, output disable, standby, automatic stand- by and reset/power-down) and synchronous (synchronous read and synchronous burst read). the dual bank architecture of the m58cr032 al- lows read/write operations in bank a, while read operations are being executed in bank b or vice versa. write operations are only allowed in one bank at a time (see table 7). see table 3, bus operations, for a summary. typ- ically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. asynchronous read. asynchronous read oper- ations read from the memory array, or specific registers (electronic signature, status register, cfi, block protection status, read configuration register status and protection register) in the command interface. a valid asynchronous bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the address is latched on the rising edge of the latch, l, input. the data inputs/out- puts will output the value, see figure 11, asyn- chronous read ac waveforms, and table 21, asynchronous read ac characteristics, for de- tails of when the output becomes valid. according to the device configuration the following read operations: electronic signature, status register, cfi, block protection status, burst con- figuration register status and protection register must be accessed as asynchronous read or as single synchronous read. asynchronous page read. asynchronous page read operations can be used to read the content of the memory array, where data is inter- nally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0 and a1 address inputs. valid bus operations are the same as asynchro- nous bus read operations but with different tim- ings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings ap- ply again. see figure 12, asynchronous page read ac waveforms and table 21, asynchro- nous read ac characteristics for details on when the outputs become valid. asynchronous page read is the default state of the device when exiting power-down or after pow- er-up. asynchronous write. bus write operations are used to write to the command interface of the memory or latch input data to be programmed. a valid bus write operation begins by setting the de- sired address on the address inputs and setting chip enable, e, and write enable, w, to v il and output enable to v ih . addresses are latched on the rising edge of l, w or e whichever occur first. commands and input data are latched on the ris- ing edge of w or e whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figures 14 and 15, write ac waveforms, and tables 23 and 24, write ac characteristics, for details of the timing require- ments. write operations are asynchronous and the clock is ignored during write. output disable. the data outputs are high im- pedance when the output enable, g, and write enable, w, are high, v ih . standby. when chip enable is high, v ih , and the program/erase controller is idle, the memory en- ters standby mode and the data inputs/outputs pins are placed in the high impedance state, inde- pendent of output enable, g, or write enable, w. for the standby current level see table 19, dc characteristics. reset/power-down. the memory is in power- down when the burst configuration register is set for power-down and rp is at v il . the power con- sumption is reduced to the power-down level, and outputs are in high impedance, independent of chip enable e, output enable g or write enable w. the memory is in reset mode when the burst configuration register is set for reset and rp is at v il . the power consumption is the same of the standby and the outputs are in high impedance. after a reset/power-down the device defaults to asynchronous page read, the status register is cleared and the burst configuration register de- faults to asynchronous page read. automatic standby. if cmos levels (v dd 0.2v) are used to drive the bus and the bus is in- active for 150ns or more in read mode, the mem- ory enters automatic standby where the internal supply current is reduced to the standby supply current, i dd2 . the data inputs/outputs will still output data if a bus read operation is in progress. the automatic standby feature is not available when the device is configured for synchronous burst mode. synchronous single read. synchronous sin- gle reads can be used to read the electronic sig- nature, status register, cfi, block protection status, burst configuration register status or
13/63 m58cr032c, m58cr032d protection register, see figure 6, for an example of a single synchronous read operation. synchronous burst read. the device also sup- ports a synchronous burst read. in this mode a burst sequence is started at the first clock edge (rising or falling according to configuration set- tings) after the falling edge of latch enable. after a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. the burst se- quence may be configured to be sequential or in- terleaved and for a length of 4 or 8 words or for continuous burst mode (see table 5, burst type definition). wrap and no-wrap modes are also supported. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. see the burst configuration register command for more details on all the possible set- tings for the synchronous burst read (see table 4). it is possible to perform burst read across bank boundaries (all banks in read array mode). table 3. bus operations note: 1. x = don't care. 2. t = transition, falling edge for l, rising or falling edge for k depending on m6 in the burst configuration register. the burst sequence is started on the first active clock edge after the falling edge of latch enable. 3. l can be tied to v ih if the valid address has been previously latched operation e g w l k rp wp dq15-dq0 asynchronous read v il v il v ih v il (3) x v ih x data output asynchronous page read v il v il v ih v il (3) x v ih x data output asynchronous write v il v ih v il v il (3) x v ih v ih data input output disable v il v ih v ih xx v ih v ih hi-z standby v ih xxx x v ih x hi-z reset / power-down x x x x x v il x hi-z synchronous read v il v il v ih t (2) t (2) v ih x data output synchronous burst read v il v il v ih t (2) t (2) v ih x data output
m58cr032c, m58cr032d 14/63 figure 6. synchronous single read operation ai90103 a20-a0 valid address l dq15-dq0 valid data not valid dq15-dq0 valid data dq15-dq0 not valid not valid not valid x latency = 4 x latency = 3 x latency = 2 not valid not valid valid data k
15/63 m58cr032c, m58cr032d burst configuration register the burst configuration register is used to config- ure the type of bus access that the memory will perform. the burst configuration register is set through the command interface. after a reset or power- up the device is configured for asynchronous page read (m15 = 1) and the power save function is disabled (m10 = 0). the burst configuration register bits are described in table 4. they spec- ify the selection of the burst length, burst type, burst x latency and the read operation. refer to figures 7 and 8 for examples of synchronous burst configurations. read select bit (m15). the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to '1', bus read operations are asynchronous; when the read select but is set to '0', bus read operations are synchronous. synchronous burst read is supported in both pa- rameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to'1' for asynchronous access. x-latency bits (m13-m11). the x-latency bits are used during synchronous bus read opera- tions to set the number of clock cycles between the address being latched and the first data be- coming available. for correct operation the x-la- tency bits can only assume the values in table 4, burst configuration register. the correspondence between x-latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. two conditions must be satisfied: (n + 1) t k t acc -t avk_cpu +t qvk_cpu t k >t kqv +t qvk_cpu where ono is the chosen x-latency configuration code, t k is the clock period, t avk_cpu is clock to address valid, l low or e low, whichever occurs last, and t qvk_cpu is the data setup time required by the system cpu. power-down bit (m10). the power-down bit is used to enable or disable the power-down func- tion. when the power-down bit is set to `0' (de- fault) the power-down function is disabled. when the power-down bit is set to `1' power-down is en- abled and the device goes into the power-down state where the i dd supply current is reduced to a typical figure of i dd2 . if this function is disabled the reset/power-down, rp, pin causes only a reset of the device and the supply current is the standby value. the recovery time after a reset/power-down, rp, pulse is sig- nificantly longer when power-down is enabled (see table 25). wait bit (m8). in burst mode the wait bit controls the timing of the wait output pin, wait. when the wait bit is '0' the wait output pin is asserted during the wait state. when the wait bit is '1' (default) the wait output pin is asserted one clock cycle before the wait state. wait is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap config- uration is selected. wait is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. burst type bit (m7). the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is '0' the memory outputs from interleaved ad- dresses; when the burst type bit is '1' (default) the memory outputs from sequential addresses. see tables 5, burst type definition, for the sequence of addresses output from a given starting address in each mode. valid clock edge bit (m6). the valid clock edge bit, m6, is used to configure the active edge of the clock, k, during synchronous burst read operations. when the valid clock edge bit is '0' the falling edge of the clock is the active edge; when the valid clock edge bit is '1' the rising edge of the clock is active. wrap burst bit (m3). the burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select between wrap and no wrap. when the wrap burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. burst length bits (m2-m0). the burst length bits set the number of words to be output during a synchronous burst read operation; 4 words, 8 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device ac- tivates the wait output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 word boundary no wait states are needed and the wait output is not activated. if the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. wait will
m58cr032c, m58cr032d 16/63 be asserted only once during a continuous burst access. see also table 5, burst type definition. m14, m9, m5 and m4 are reserved for future use. table 4. burst configuration register bit description value description m15 read select 0 synchronous burst read 1 asynchronous page read (default at power-on) m14 reserved m13-m11 x-latency (2) 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 reserved other configurations reserved m10 power-down (3) 0 power-down disabled 1 power-down enabled m9 reserved m8 wait 0 wait is active during wait state 1 wait is active one data cycle before wait state (default) m7 burst type 0 interleaved 1 sequential (default) m6 valid clock edge 0 falling burst clock edge 1 rising burst clock edge m5-m4 reserved m3 wrapping 0 wrap 1 no wrap m2-m0 burst length 001 4 words 010 8 words 111 continuous (m7 must be set to `1')
17/63 m58cr032c, m58cr032d table 5. burst type definition mode start address 4 words 8 words continuo us burst sequential interleaved sequential interleaved wrap 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... ... 60 60-61-62-63-64-65-66... 61 61-62-63-wait-64-65-66... 62 62-63-wait-wait-64-65-66... 63 63-wait-wait-wait-64-65- 66... sequential interleaved sequential interleaved no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7... 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5-6-7-8... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9... ... 7 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13... ... 60 60-61-62-63 60-61-62-63-64-65-66- 67 60-61-62-63-64-65-66... 61 61-62-63-wait-64 61-62-63-wait-64-65- 66-67-68 61-62-63-wait-64-65-66... 62 62-63-wait- wait-64-65 62-63-wait-wait-64- 65-66-67-68-69 62-63-wait-wait-64-65-66... 63 63-wait-wait- wait-64-65-66 63-wait-wait-wait- 64-65-66-67-68-69-70 63-wait-wait-wait-64-65- 66...
m58cr032c, m58cr032d 18/63 figure 7. x-latency configuration sequence figure 8. wait configuration sequence ai90105 a20-a0 valid address k l dq15-dq0 valid data valid data dq15-dq0 valid data dq15-dq0 valid data valid data valid data x latency = 4 x latency = 3 x latency = 2 valid data valid data valid data ai90106 a20-a0 valid address k l dq15-dq0 valid data wait m8 = '0' wait m8 = '1' valid data not valid valid data e g
19/63 m58cr032c, m58cr032d command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time during, to monitor the progress of the operation, or the pro- gram/erase states. see appendix c, tables 36 and 37, command interface states - lock and modify tables, for a summary of the command in- terface. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will reset the de- vice to read mode. refer to table 6, commands, in conjunction with the text descriptions below. read command. the read command returns the addressed bank to read mode. one bus write cycle is required to issue the read command and return the ad- dressed bank to read mode. subsequent read operations will read the addressed location and output the data. a read command can be issued in one bank while programming or erasing in the other bank. however if a read command is issued to a bank currently executing a program or erase operation the command will be ignored. when a device reset occurs, the memory defaults to read mode. read status register command a bank's status register indicates when a pro- gram or erase operation is complete and the suc- cess or failure of operation itself. issue a read status register command to read the status reg- ister content of the addressed bank. the status of the other bank is not affected by the command. the read status register command can be is- sued at any time, even during program or erase operations. the following read operations output the content of the status register of the addressed bank. the status register is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. see table 15 for the description of the status register bits. this mode supports asynchronous or single synchronous reads only. read electronic signature command the read electronic signature command reads the manufacturer and device codes and the block locking status, or the protection register. the read electronic signature command consists of one write cycle to an address within the bottom bank. a subsequent read operation in the address of the bottom bank will output the manufacturer code, the device code, the protection status of blocks of the bottom bank, the die revision code, the protection register, or the read configuration register (see table 11). if the first write cycle of read electronic signature command is issued to an address within the top bank, a subsequent read operation in an address of the top bank will output the protection status of blocks of the top bank. the status of the other bank is not affected by the command (see table 7). this mode supports asynchronous or single synchronous reads only. see tables 8, 9, 10 and 11 for the valid addresses. read cfi query command the read cfi query command is used to read data from the common flash interface (cfi) memory area, located in the bottom bank. one bus write cycle, addressed to the bottom bank, is required to issue the read query command. once the command is issued subsequent bus read operations in the bottom bank read from the common flash interface memory area. the sta- tus of the top bank is not affected by the command (see table 7). after issuing a read cfi query command, a read command should be issued to return the bank to read mode. see appendix b, common flash interface, tables 29, 30, 31, 32, 33, 34 and 35 for details on the in- formation contained in the common flash inter- face memory area. clear status register command the clear status register command can be used to reset (set to `0') bits 1, 3, 4 and 5 in the status register of the addressed bank'. one bus write cy- cle is required to issue the clear status register command. after the clear status register com- mand the bank returns to read mode. the bits in the status register do not automatical- ly return to `0' when a new program or erase com- mand is issued. the error bits in the status register should be cleared before attempting a new program or erase command. block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to '1'. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. it is not necessary to pre-program the block as the pro-
m58cr032c, m58cr032d 20/63 gram/erase controller does it automatically before erasing. two bus write cycles are required to issue the command. n the first bus cycle sets up the erase command. n the second latches the block address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write erase confirm (d0h), status register bits b4 and b5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register until a read command is issued. during erase operations the bank containing the block being erased will only accept the read sta- tus register command and the program/erase suspend command, all other commands will be ig- nored. typical erase times are given in table 12, program, erase times and program/erase endur- ance cycles. see appendix b, figure 22, block erase flowchart and pseudo code, for a suggested flowchart for using the block erase command. bank erase command the bank erase command can be used to erase a bank. it sets all the bits within the selected bank to '1'. all previous data in the bank is lost. the bank erase command will ignore any protected blocks within the bank. if the bank is protected then the erase operation will abort, the data in the bank will not be changed and the status register will output the error. two bus write cycles are required to issue the command. n the first bus cycle sets up the bank erase command. n the second latches the bank address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write bank erase confirm (d0h), status register bits b4 and b5 are set and the command aborts. erase aborts if re- set turns to v il . as data integrity cannot be guar- anteed when the erase operation is aborted, the bank must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register until a read command is issued. during erase operations the bank being erased will only accept the read status register com- mand and the program/erase suspend command, all other commands will be ignored. typical erase times are given in table 12, program, erase times and program/erase endurance cycles. program command the memory array can be programmed word-by- word. only one bank can be programmed at any one time. the other bank must be in read mode or erase suspend. two bus write cycles are re- quired to issue the program command. n the first bus cycle sets up the program command. n the second latches the address and the data to be written and starts the program/erase controller. after programming has started, read operations in the bank being programmed output the status register content. during program operations the bank being pro- grammed will only accept the read status regis- ter command and the program/erase suspend command. typical program times are given in ta- ble 12, program, erase times and program/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. see appendix b, figure 18, program flowchart and pseudo code, for the flowchart for using the program command. double word program command this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. the two words must differ only for the address a0. only one bank can be programmed at any one time. the other bank must be in read mode or erase suspend. programming should not be attempted when v pp is not at v pph . the command can be executed if v pp is below v pph but the result is not guaranteed. three bus write cycles are necessary to issue the double word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller.
21/63 m58cr032c, m58cr032d read operations in the bank being programmed output the status register content after the pro- gramming has started. during double word program operations the bank being programmed will only accept the read sta- tus register command and the program/erase suspend command. typical program times are given in table 12, program, erase times and pro- gram/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. see appendix b, figure 19, double word program flowchart and pseudo code, for the flowchart for using the double word program command. quadruple word program command this feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. the first write cycle must be addressed to the bank to be programmed. only one bank can be programmed at any one time. the other bank must be in read mode or erase suspend. programming should not be attempted when v pp is not at v pph . the command can be executed if v pp is below v pph but the result is not guaranteed. five bus write cycles are necessary to issue the quadruple word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written. n the fourth bus cycle latches the address and the data of the third word to be written. n the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. read operations to the bank being programmed output the status register content after the pro- gramming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. during quadruple word program operations the bank being programmed will only accept the read status register command and the program/erase suspend command. typical program times are given in table 12, program, erase times and pro- gram/erase endurance cycles. see appendix b, figure 20, quadruple word pro- gram flowchart and pseudo code, for the flow- chart for using the quadruple word program command. program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. one bus write cycle is required to issue the program/erase command and pause the program/erase control- ler. the command must be addressed to the bank containing the program or erase operation. during program/erase suspend the command in- terface will accept the program/erase resume, read, read status register, read electronic sig- nature and read cfi query commands. addition- ally, if the suspend operation was erase then the program, block lock, block lock-down or protec- tion program commands will also be accepted. the block being erased may be protected by issu- ing the block lock, block lock-down or protection program commands. only the blocks not being erased may be read or programmed correctly. when the program/erase resume command is is- sued the operation will complete. during a program/erase suspend, the device can be placed in a pseudo-standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix b, figure 21, program suspend & resume flowchart and pseudo code, and figure 23, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/ erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend command has paused it. one bus write cycle is required to issue the command. the command must be addressed to the bank containing the program or erase opera- tion. once the command is issued subsequent bus read operations read the status register. if a program command is issued during a block erase suspend, then the erase cannot be re- sumed until the programming operation has com- pleted. it is possible to accumulate suspend operations. for example: suspend an erase oper- ation, start a programming operation, suspend the programming operation then read the array. see appendix b, figure 21, program suspend & re- sume flowchart and pseudo code, and figure 23, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/erase resume command.
m58cr032c, m58cr032d 22/63 protection register program command the protection register program command is used to program the 64 bit user one-time-pro- grammable (otp) segment of the protection reg- ister. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to `1'. the user can only program the bits to `0'. two write cycles are required to issue the protec- tion register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the segment can be protected by programming bit 1 of the protection lock register. bit 1 of the pro- tection lock register protects bit 2 of the protec- tion lock register. programming bit 2 of the protection lock register will result in a permanent protection of the security block (see figure 5, se- curity block and protection register memory map). attempting to program a previously protect- ed protection register will result in a status reg- ister error. the protection of the protection register and/or the security block is not revers- ible. the protection register program cannot be sus- pended. see appendix b, figure 25, protection register program flowchart and pseudo code, for a flowchart for using the protection register program command. block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. n the first bus cycle sets up the block lock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 14 shows the lock status after issuing a block lock command. the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a blocks unlock command. refer to the section, block locking, for a detailed explanation. see appendix b, figure 24, locking operations flowchart and pseudo code, for a flowchart for using the lock command. block unlock command the blocks unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to is- sue the blocks unlock command. n the first bus cycle sets up the block unlock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 13 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and ap- pendix b, figure 24, locking operations flow- chart and pseudo code, for a flowchart for using the unlock command. block lock-down command a locked block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock com- mand. two bus write cycles are required to issue the block lock-down command. n the first bus cycle sets up the block lock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table. 14 shows the lock status af- ter issuing a block lock-down command. refer to the section, block locking, for a detailed explana- tion and appendix b, figure 24, locking opera- tions flowchart and pseudo code, for a flowchart for using the lock-down command. set burst configuration register command. the set burst configuration register command is used to write a new value to the burst configura- tion control register which defines the burst length, type, x latency, synchronous/asynchro- nous read mode and the valid clock edge config- uration. two bus write cycles are required to issue the set burst configuration register command. the first cycle writes the setup command and the address corresponding to the set burst configuration reg- ister content. the second cycle writes the burst configuration register data and the confirm com- mand. once the command is issued the memory returns to read mode as if a read memory array command had been issued.
23/63 m58cr032c, m58cr032d the value for the burst configuration register is always presented on a0-a15. m0 is on a0, m1 on a1, etc.; the other address bits are ignored. table 6. commands note: 1. x = don't care, ra=read address, rd=read data, srd=status register data, esa= electronic signature address, id=identifier (manufacture and device code), qa=query address, qd=query data, ba=block address, pa=program address, pd=program data, pra=protection register address, prd=protection register data, bcra=burst configuration register address, bcrd=burst configuration register data. 2. the signature addresses are listed in tables 8, 9 and 10. 3. program addresses 1 and 2 must be consecutive addresses differing only for a0. 4. program addresses 1,2,3 and 4 must be consecutive addresses differing only for a0 and a1. commands cycles bus write operations 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle op. add data op. add data op. add data op. add data op. add data read memory array 1+ write bka ffh read ra rd read status register 1+ write bka 70h read bka srd read electronic signature 1+ write esa 90h read esa (2) idh read cfi query 1+ write qa 98h read qa qd block erase 2 write ba 20h write ba d0h bank erase 2 write bka 80h write bka d0h program 2 write pa 40h or 10h write pa pd double word program (3) 3 write pa1 30h write pa1 pd1 write pa2 pd2 quadruple word program (4) 5 write pa1 55h write pa1 pd1 write pa2 pd2 write pa3 pd3 write pa4 pd4 clear status register 1 write bka 50h program/erase suspend 1 write bka b0h program/erase resume 1 write bka d0h block lock 2 write ba 60h write ba 01h block unlock 2 write ba 60h write ba d0h block lock-down 2 write ba 60h write ba 2fh protection register program 2 write pra c0h write pra prd set burst configuration register 2 write bcra 60h write bcra 03h
m58cr032c, m58cr032d 24/63 table 7. dual bank operations note: 1. for detailed description of command see table 6, 36 and 37. 2. there is a status register for each bank; status register indicates bank state, not p/e.c. status. 3. command must be written to an address within the block targeted by that command. table 8. read electronic signature note: 1. addresses are latched on the rising edge of l input. 2. esa means electronic signature address (see read electronic signature) table 9. read block protection note: 1. addresses are latched on the rising edge of l input. 2. a locked block can only be unlocked with wp at v ih. 3. ba means block address. first cycle command address should indicate the bank of the block address. status of one bank commands allowed in the other bank read array read status read cfi program erase/ erase resume program suspend erase suspend lock unlock idle yes yes yes yes yes yes yes yes reading programming yes yes yes yes erasing yes yes yes yes program suspended yesyesyesyes erase suspended yes yes yes yes yes yes code device e g w a1 a0 other addresses dq15-dq0 manufacturer code v il v il v ih v il v il esa (2) 0020h device code m58cr032c v il v il v ih v il v ih esa (2) 88c8h m58cr032d v il v il v ih v il v ih esa (2) 88c9h block status e g w a0 a1 other address dq15-dq0 locked block v il v il v ih v il v ih ba (3) 0001 unlocked block v il v il v ih v il v ih ba (3) 0000 locked and locked-down block v il v il v ih v il v ih ba (3) 0003 unlocked and locked-down v il v il v ih v il v ih ba (3) 0002
25/63 m58cr032c, m58cr032d table 10. read protection register note: 1. addresses are latched on the rising edge of l input. 2. x = don't care. table 11. identifier codes note: drc=di e revision code, bcr=burst configuration register, lpr= lock protection register, pr=protection register (unique device number and user programmable otp). word e g w a20-16 a15-8 a7-0 dq15-8 dq7-3 dq2 dq1 dq0 lock v il v il v ih x (2) x (2) 80h 00h 00000b security prot.data otp prot.data 0 unique id 0 v il v il v ih x (2) x (2) 81h id data id data id data id data id data unique id 1 v il v il v ih x (2) x (2) 82h id data id data id data id data id data unique id 2 v il v il v ih x (2) x (2) 83h id data id data id data id data id data unique id 3 v il v il v ih x (2) x (2) 84h id data id data id data id data id data otp 0 v il v il v ih x (2) x (2) 85h otp data otp data otp data otp data otp data otp 1 v il v il v ih x (2) x (2) 86h otp data otp data otp data otp data otp data otp 2 v il v il v ih x (2) x (2) 87h otp data otp data otp data otp data otp data otp 3 v il v il v ih x (2) x (2) 88h otp data otp data otp data otp data otp data code address (h) data (h) manufacturer code bank address + 00 0020 device code top (m58cr032c) bank address + 01 88c8 bottom (m58cr032d) 88c9 block protection lock bank address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 die revision code bank address + 03 drc burst configuration register bank address + 05 bcr lock protection register bank address + 80 lpr protection register bank address + 81 bank address + 88 pr
m58cr032c, m58cr032d 26/63 table 12. program, erase times and program, erase endurance cycles note: 1. t a = 40 to 85 c; v dd = 1.65v to 2v; v ddq = 1.65v to 3.3v. 2. the difference between preprogrammed and not preprogrammed is not significant (?30ms). 3. excludes the time needed to execute the command sequence. parameter condition min typ typical after 100k w/e cycles max unit v pp =v dd parameter block (4 kword) erase (2) 0.3 1 2.5 s main block (32 kword) erase preprogrammed 0.8 3 4 s not preprogrammed 1.1 4 s bank a (8mbit) erase preprogrammed 5.5 s not preprogrammed 9 s bank b (24mbit) erase preprogrammed 16.5 s not preprogrammed 27 s parameter block (4 kword) program (3) 40 ms main block (32 kword) program (3) 300 ms word program (3) 10 10 100 m s program suspend latency 5 10 m s erase suspend latency 5 20 m s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v pp =v pph parameter block (4 kword) erase 0.3 2.5 s main block (32 kword) erase 0.9 4 s bank a (8mbit) erase 6.5 s bank b (24mbit) erase 19.5 s 4mbit program quadruple word 510 ms word/ double word/ quadruple word program (3) 8 100 m s parameter block (4 kword) program (3) quadruple word 8 ms word 32 ms main block (32 kword) program (3) quadruple word 64 ms word 256 ms program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles
27/63 m58cr032c, m58cr032d block locking the m58cr032 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. n lock/unlock - this first level allows software- only control of block locking. n lock-down - this second level requires hardware interaction before locking can be changed. n v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. for all devices the protection status of each block can be set to locked, unlocked, and lock-down. table 14, defines all of the possible protection states (wp, dq1, dq0), and appendix b, figure 24, shows a flowchart for the locking operations. reading a block's lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subse- quent reads at the address specified in table 9, will output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when enter- ing lock-down. dq1 indicates the lock-down sta- tus and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software com- mands. an unlocked block can be locked by issu- ing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked- down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp input pin. when wp=0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wp=1 (v ih ) the lock-down function is disabled (1,1,1) and locked-down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while wp remains high. when wp is low , blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp was high. device reset or power-down resets all blocks , including those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix c, com- mand interface state table, for detailed informa- tion on which commands are valid during erase suspend.
m58cr032c, m58cr032d 28/63 table 13. block lock status table 14. lock status note: 1. the lock status is defined by the write protect pin and by dq1 (`1' for a locked-down block) and dq0 (`1' for a locked block) as read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. item address data block lock configuration xx002 lock block is unlocked dq0=0 block is locked dq0=1 block is locked-down dq1=1 current protection status (1) (wp, dq1, dq0) next protection status (1) (wp, dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
29/63 m58cr032c, m58cr032d status register the m58cr032 has two status registers, one for each bank. the status registers provide informa- tion on the current or previous program or erase operations executed in each bank. the various bits convey information and errors on the opera- tion. issue a read status register command to read the status register content of the addressed bank, refer to read status register command section for more details. to output the contents, the status register is latched on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable re- turns to v ih . either chip enable or output enable must be toggled to update the latched data. bus read operations from any address within the bank, always read the status register during pro- gram and erase operations. the bits in the status register are summarized in table 15, status register bits. refer to table 15 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive in the addressed bank. when the program/erase controller status bit is low (set to `0'), the pro- gram/erase controller is active; when the bit is high (set to `1'), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high . during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block lock status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended or is going to be suspended in the addressed block. when the erase suspend status bit is high (set to `1'), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). bit 7 is set within 30 m s of the program/erase sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. when the erase status bit is high (set to `1'), the program/ erase controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. the erase sta- tus bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program failure. when the program status bit is high (set to `1'), the pro- gram/erase controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. the program status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v pp status (bit 3). the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can oc- cur if v pp becomes invalid during an operation. when the v pp status bit is low (set to `0'), the volt- age on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to `1'), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and pro- gram and erase operations cannot be performed. once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended in the addressed block. when the program suspend status bit is high (set to `1'), a program/erase suspend command has
m58cr032c, m58cr032d 30/63 been issued and the memory is waiting for a pro- gram/erase resume command. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). bit 2 is set within 5 m s of the program/erase suspend command being issued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to `1'), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value must be masked. note: refer to appendix b, flowcharts and pseudo codes, for using the status register. table 15. status register bits note: logic level '1' is high, '0' is low. bit name logic level definitio n 7 p/e.c. status '1' ready '0' busy 6 erase suspend status '1' suspended '0' in progress or completed 5 erase status '1' erase error '0' erase success 4 program status '1' program error '0' program success 3 v pp status '1' v pp invalid, abort '0' v pp ok 2 program suspend status '1' suspended '0' in progress or completed 1 block protection status '1' program/erase on protected block, abort '0' no operation to protected blocks 0 reserved
31/63 m58cr032c, m58cr032d maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 16. absolute maximum ratings note: 1. minimum voltage may undershoot to 2v during transition and for less than 20ns during transitions. symbol parameter value unit t a ambient operating temperature 40 to 85 c t bias temperature under bias 40 to 125 c t stg storage temperature 55 to 155 c v io (1) input or output voltage 0.5 to v ddq +0.5 v v dd ,v ddq supply voltage 0.5 to 2.7 v v pp program voltage 0.5 to 13 v
m58cr032c, m58cr032d 32/63 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 17, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 17. operating and ac measurement conditions figure 9. ac measurement i/o waveform figure 10. ac measurement load circuit table 18. capacitance note: sampled only, not 100% tested. m58cr032c, m58cr032d parameter 85 100 120 units min max min max min max v dd supply voltage 1.8 2.0 1.65 2.0 1.65 2.0 v v ddq supply voltage 1.8 3.3 1.65 3.3 1.65 3.3 v ambient operating temperature 40 85 40 85 40 85 c load capacitance (c l ) 30 30 30 pf input rise and fall times 4 4 4 ns input pulse voltages 0tov ddq 0tov ddq 0tov ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ddq /2 v ai90007 v ddq 0v v ddq /2 ai90008 v ddq /2 out c l c l includes jig capacitance 3.3k w 1n914 device under test symbol parameter test condition min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf
33/63 m58cr032c, m58cr032d table 19. dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 m a i lo output leakage current 0v v out v ddq 1 m a i dd1 supply current asynchronous read (f=6mhz) e=v il ,g=v ih 36ma supply current synchronous read (f=40mhz) 4 word 6 13 ma 8 word 8 14 ma continuous 6 10 ma i dd2 supply current (reset) rp = v ss 0.2v 210 m a i dd3 supply current (standby) e=v dd 0.2v 10 50 m a i dd4 (1) supply current (program) v pp =v pph 815ma v pp =v dd 10 20 ma supply current (erase) v pp =v pph 815ma v pp =v dd 10 20 ma i dd5 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 13 26 ma program/erase in one bank, synchronous read in another bank 16 30 ma i dd6 (1) supply current program/ erase suspended (standby) e=v dd 0.2v 10 50 m a i pp1 (1) v pp supply current (program) v pp =v pph 25ma v pp =v dd 0.2 5 m a v pp supply current (erase) v pp =v pph 25ma v pp =v dd 0.2 5 m a i pp2 v pp supply current (read) v pp =v pph 100 400 m a v pp v dd 0.2 5 m a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 m a
m58cr032c, m58cr032d 34/63 table 20. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage 0.5 0.4 v v ih input high voltage v ddq 0.4 v ddq + 0.4 v v ol output low voltage i ol = 100 m a 0.1 v v oh output high voltage i oh = 100 m av ddq 0.1 v v pp1 v pp program voltage-logic program, erase 1 1.8 1.95 v v pph v pp program voltage factory program, erase 11.4 12 12.6 v v pplk program or erase lockout 0.9 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v
35/63 m58cr032c, m58cr032d figure 11. asynchronous read ac waveforms ai90109 tavav tavqv telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid data a0-a20 valid address valid address l tellh tllqv tlllh tavlh tlhax note: write enable (w) = high.
m58cr032c, m58cr032d 36/63 figure 12. asynchronous page read ac waveforms ai90148 a2-a20 e g a0-a1 valid address l dq0-dq15 valid address valid address valid address valid address valid data valid data valid data valid data tlhax tavlh tllqv tllqv1 tavqv1 tglqv
37/63 m58cr032c, m58cr032d table 21. asynchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . symbol alt parameter test condition m58cr032 unit 85 100 120 min max min max min max t avav t rc address valid to next address valid e=v il ,g=v il 85 100 120 ns t avlh t avavdh address valid to latch enable high g=v ih 10 10 10 ns t avqv t acc address valid to output valid (random) e=v il ,g=v il 85 100 120 ns t avqv1 t page address valid to output valid (page) e=v il ,g=v il 35 45 45 ns t ehqx t oh chip enable high to output transition g=v il 000ns t ehqz (1) t hz chip enable high to output hi-z g=v il 20 20 20 ns t ellh t elavdh chip enable low to latch enable high e=v il ,g=v ih 10 10 10 ns t elqv (2) t ce chip enable low to output valid g=v il 85 100 120 ns t elqx (1) t lz chip enable low to output transition g=v il 000ns t ghqx t oh output enable high to output transition e=v il 000ns t ghqz (1) t df output enable high to output hi-z e=v il 20 20 20 ns t glqv (2) t oe output enable low to output valid e=v il 25 25 35 ns t glqx (1) t olz output enable low to output transition e=v il 000ns t lhax t avdhax latch enable high to address transition e=v il ,g=v ih 10 10 10 ns t lllh t avdlavdh latch enable pulse width e=v il ,g=v ih 10 10 10 ns t llqv t avdlqv latch enable low to output valid (random) e=v il 85 100 120 ns t llqv1 latch enable low to output valid (page) e=v il 35 45 45 ns
m58cr032c, m58cr032d 38/63 figure 13. synchronous burst read ai90110 dq0-dq15 e g a0-a20 l wait k valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkaxh tkhqx tkhqv valid data valid note 1 note 2 note 3 tkhqv tkhqv tehqx tehqz tghqx tghqz tkhkh tkhqx tkhkl tklkh note: 1. the number of clock cycles to be inserted depends upon the x-latency set in the burst configuration register. 2. wait signal can be configured to be active during wait state or one cycle below wait state. 3. wait signal is asserted only when burst length is configured as continuous (see burst read section for further information).
39/63 m58cr032c, m58cr032d table 22. synchronous burst read ac characteristics note: for other timings please refer to table 21, asynchronous read ac characteristics symbol alt parameter test condit ion m58cr032 unit 85 100 120 min max min max min max t avkh t avclkh address valid to clock high 777ns t elkh t celclkh chip enable low to clock high 777ns t khkh t clk clock period 18 18 25 ns t khax t clkhax clock high to address transition e=v il ,g=v ih 10 10 10 ns t khkl t clkhclkl clock high to clock low 5 5 5 ns t klkh t clklclkh clock low to clock high 5 5 5 ns t khqv t clkhqv clock to data valid clock to wait valid e=v il ,g=v il 14 14 18 ns t khqx t clkhqx clock to output transition clock to wait transition e=v il 444ns t llkh t avdlclkh latch enable low to clock high 777ns
m58cr032c, m58cr032d 40/63 figure 14. write ac waveforms, write enable controlled ai90111 tlhax dq0-dq15 l g tavlh data valid a0-a20 e tlllh telwl w address valid tdvwh twhdx twlwh tellh twhgl v dd tvdhel twhll wp twpvwh twhwpv v pp tvpphwh v pp1 v pph twhvppl tavav valid twheh twhwl
41/63 m58cr032c, m58cr032d table 23. write ac characteristics, write enable controlled symbol alt parameter m58cr032 unit 85 100 120 min max min max min max t avav t wc address valid to next address valid 85 100 120 ns t avlh address valid to latch enable high 10 10 10 ns t dvwh t ds input valid to write enable high 40 40 40 ns t ellh chip enable low to latch enable high 10 10 10 ns t elwl t cs chip enable low to write enable low 0 0 0 ns t lhax latch enable high to address transition 10 10 10 ns t lllh latch enable pulse width 10 10 10 ns t vdhel t vcs v dd high to chip enable low 50 50 50 m s t vpphwh v pp high to write enable high 200 200 200 ns t whdx t dh write enable high to input transition 0 0 0 ns t wheh t ch write enable high to chip enable high 0 0 0 ns t whgl t oeh write enable high to output enable low 0 0 0 ns t whll write enable high to latch enable low 0 0 0 ns t whvppl write enable high to v pp low 200 200 200 ns t whwl t wph write enable high to write enable low 30 30 30 ns t whwpv write enable high to write protect valid 200 200 200 ns t wlwh t wp write enable low to write enable high 50 50 50 ns t wpvwh write protect valid to write enable high 200 200 200 ns
m58cr032c, m58cr032d 42/63 figure 15. write ac waveforms, chip enable controlled tlhax dq0-dq15 l g tavlh data valid a0-a20 e tlllh teleh w address valid tdveh tehdx tehwh tellh twhll twlel ai90112 v dd tvdhel wp twpheh tehwpl v pp tvppheh v pp1 v pp2 tehvppl tavav tlheh
43/63 m58cr032c, m58cr032d table 24. write ac characteristics, chip enable controlled symbol alt parameter m58cr032 unit 85 100 120 min max min max min max t avav t wc address valid to next address valid 85 100 120 ns t avlh address valid to latch enable high 10 10 10 ns t dveh t ds input valid to chip enable high 40 40 40 ns t ehdx t dh chip enable high to input transition 0 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 30 ns t ehwh t wh chip enable high to write enable high 0 0 0 ns t eleh t cp chip enable low to chip enable high 60 60 60 ns t ellh chip enable low to latch enable high 10 10 10 ns t lhax latch enable high to address transition 10 10 10 ns t lheh latch enable high to chip enable high 10 10 10 ns t lllh latch enable pulse width 10 10 10 ns t vdhel t vcs v dd high to chip enable low 50 50 50 m s t vppheh v pp high to chip enable high 200 200 200 ns t ehvppl chip enable high to v pp low 200 200 200 ns t ehwpl chip enable high to write protect low 200 200 200 ns t wlel t ws chip enable low to chip enable low 0 0 0 ns t wpheh write protect high to chip enable high 200 200 200 ns
m58cr032c, m58cr032d 44/63 figure 16. reset and power-up ac waveforms table 25. reset and power-up ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 100ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initializat ion during power-up or system reset. symbol parameter test condition min unit t plph (1,2) rp pulse width 50 ns t plwl t plel t plgl reset low to device enabled during program and erase 10/20 m s other conditions 80 ns t vdhph (3) supply valid to reset high 50 m s ai90013b w, rp e, g vdd, vddq tvdhph tplwl tplel tplgl tplph power-up reset
45/63 m58cr032c, m58cr032d package mechanical figure 17. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, bottom view package outline note: drawing is not to scale. table 26. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.010 1.200 0.0398 0.0472 a1 0.250 0.400 0.0098 0.0157 a2 0.790 0.0311 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.500 6.400 6.600 0.2559 0.2520 0.2598 d1 5.250 0.2067 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 4.500 0.1772 e 0.750 0.0295 fd 0.625 0.0246 fe 2.750 0.1083 sd 0.375 0.0148 e1 e d1 d a2 a1 a bga-z20 ddd e e sd b fe fd ball oa1o
m58cr032c, m58cr032d 46/63 part numbering table 27. ordering information scheme devices are shipped from the factory with the memory content bits erased to '1'. for a list of available options (speed, package, etc....) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m58cr032c 85 zb 6 t device type m58 architecture c = dual bank, burst mode operating voltage r=v dd = 1.65v to 2.0v, v ddq = 1.65v to 3.3v device function 032c = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, top boot 032d = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, bottom boot speed 85 = 85 ns 100 = 100 ns 120 = 120 ns package zb = tfbga56: 0.75 mm pitch temperature range 6=40to85 c optio n t = tape & reel packing
47/63 m58cr032c, m58cr032d revision history table 28. document revision history date version revision details april 2001 -01 first issue 23-oct-2001 -02 85ns speed class added, document classified as preliminary data 21-mar-2002 -03 document completely revised. changes in cfi content, program and erase times table and dc characteristics table 06-sep-2002 3.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0). latch enable, l, logic level modified during asynchronous read/write operations as shown in table 3, bus operations. first x-latency formula modified together with meaning of t avk_cpu parameter in formula (under burst configuration register paragraph). minimum v dd and v ddq supply voltages reduced to 1.8v for 85ns class speed in table 17, operating and ac measurement conditions. `number of identical-size erase block' parameters modified in table 32, device geometry definition.
m58cr032c, m58cr032d 48/63 appendix a. common flash interface the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 29, 30, 31, 32, 33, 34 and 35 show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 35, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. issue a read command to return to read mode. table 29. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-sections detailed in tables 30, 31, 32, 33, 34 and 35. query data are always presented on the lowest order data outputs. table 30. cfi query identification string note: query data are always presented on the lowest - order data outputs (adq0-adq7) only. adq8-adq15 are `0'. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 80h security code area lock protection register unique device number and user programmable otp offset sub-section name description value 00h 0020h manufacturer code st 01h 88c8h 88c9h device code (m58cr032c/d) top bottom 02h reserved reserved 03h reserved reserved 04h-0fh reserved reserved 10h 0051h query unique ascii string oqryo oqo 11h 0052h oro 12h 0059h oyo 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table (see table 32) p = 39h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table na 1ah 0000h
49/63 m58cr032c, m58cr032d table 31. cfi query system interface information table 32. device geometry definition offset data description value 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 1dh 0017h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1eh 00c0h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 12v 1fh 0004h typical time-out per single byte/word program = 2 n m s 16 m s 20h 0003h typical time-out for quadruple word program = 2 n m s 8 m s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0003h maximum time-out for word program = 2 n times typical 128 m s 24h 0004h maximum time-out for quadruple word = 2 n times typical 128 m s 25h 0002h maximum time-out per individual block erase = 2 n times typical 4s 26h 0000h maximum time-out for chip erase = 2 n times typical na offset word mode data description value 27h 0016h device size = 2 n in number of bytes 4 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 byte 2ch 0002h number of erase block regions within the device bit 7 to 0 = x = number of erase block regions it specifies the number of regions within the device containing one or more contiguous erase blocks of the same size. 2
m58cr032c, m58cr032d 50/63 table 33. primary algorithm-specific extended query table m58cr032c 2dh 2eh 003eh 0000h region 1 information number of identical-size erase block = 003eh+1 63 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 bytes 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase block = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 bytes 8 kbyte 35h 38h 0000h reserved for future raise block region information na m58cr032d 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 bytes 8 kbyte 31h 32h 003eh 0000h region 2 information number of identical-size erase block = 003eh+1 63 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 bytes 64 kbyte 35h 38h 0000h reserved for future raise block region information na offset data description value (p)h = 39h 0050h primary algorithm extended query table unique ascii string aprio opo 0052h oro 0049h oio (p+3)h = 3ch 0031h major version number, ascii o1o (p+4)h = 3dh 0030h minor version number, ascii o0o (p+5)h = 3eh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 9 simultaneous operation supported (1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are `0'. if bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h 0000h (p+8)h 0000h offset word mode data description value
51/63 m58cr032c, m58cr032d table 34. burst read information (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are `0' ye s (p+a)h = 43h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are `0' ye s ye s (p+b)h 0000h (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8v (p+d)h = 46h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12v (p+e)h = 47h (p+f)h (p+10)h (p+11)h (p+12)h 0000h reserved offset data description value (p+13)h = 4ch 0003h page-mode read capability bits 0-7 'n' such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page-mode data output width. 8 byte (p+14)h = 4dh 0003h number of synchronous mode read configuration fields that follow. 3 (p+15)h = 4eh 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 'n' such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. this field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+16)h = 4fh 0002h synchronous mode read capability configuration 2 8 (p+17)h = 50h 0007h synchronous mode read capability configuration 3 cont. (p+18)h = 51h 0036h max operating clock frequency (mhz) 54 mhz offset data description value
m58cr032c, m58cr032d 52/63 table 35. security code area (p+19)h = 52h 0001h supported handshaking signal (wait pin) bit 0 during synchronous read (1 = yes, 0 = no) bit 1 during asynchronous read (1 = yes, 0 = no) ye s no offset data description 80h lpr lock protection register bit 0: st programmed, value 0 bit 1: otp protection and bit 2 protection bit bit 2: security block protection bit bits 3 - 15 reserved 81h id data 64 bits: unique device number 82h 83h 84h 85h otp data 64 bits: user programmable otp 86h 87h 88h offset data description value
53/63 m58cr032c, m58cr032d appendix b. flowcharts and pseudo codes figure 18. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write 40h or 10h ai090014b start write address & data read status register yes no b7=1 yes no b3=0 no b4=0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0x40) ; /*or writetoflash (any_address, 0x10) ; */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no b1=0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
m58cr032c, m58cr032d 54/63 figure 19. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. write 30h ai090015b start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (any_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
55/63 m58cr032c, m58cr032d figure 20. quadruple word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differing only for bits a0 and a1. write 55h ai05283 start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (any_address, 0x55) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
m58cr032c, m58cr032d 56/63 figure 21. program suspend & resume flowchart and pseudo code write 70h ai90016b read status register yes no b7 = 1 yes no b2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b2==0) /*program completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
57/63 m58cr032c, m58cr032d figure 22. block erase flowchart and pseudo code note: if an error is found, the status register must be cleared before further program/erase operations. write 20h ai90017b start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4, b5 = 1 v pp invalid error (1) command sequence error (1) no no b5 = 0 erase error (1) end yes no b1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (any_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.b7== 0) ; do { status_register=readflash (any_address) ; /* e or g must be toggled*/ if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; }
m58cr032c, m58cr032d 58/63 figure 23. erase suspend & resume flowchart and pseudo code write 70h ai90018b read status register yes no b7 = 1 yes no b6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b6==0) /*erase completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
59/63 m58cr032c, m58cr032d figure 24. locking operations flowchart and pseudo code write 01h, d0h or 2fh ai05281 read block lock states yes no locking change confirmed? start write 60h locking_operation_command (address, lock_operation) { writetoflash (any_address, 0x60) ; /*configuration setup*/ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (any_address, 0xff) ; /*reset to read array mode*/ } write ffh write 90h end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (any_address, 0x90) ;
m58cr032c, m58cr032d 60/63 figure 25. protection register program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write c0h ai05282 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0xc0) ; do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
61/63 m58cr032c, m58cr032d appendix c. command interface state tables table 36. command interface states - lock table note: ps = program suspend, es = erase suspend. current state of other bank current state of the current bank command input to the current bank (and next state of the current bank) mode state others read array (ffh) erase confi rm p/e resume unlock confi rm (d0h) read status register (70h) clear status register (50h) read electronic signature (90h) read cfi query (98h) block lock unlock lock-down setup set bcr setup (60h) block lock confirm (01h) block lock- down confi rm (2fh) set bcr confirm (03h) any state read array see modify tabl e read array read array read status register readarray read elect. sign. read cfi block lock, unlock, lock-down, set bcr setup read array read array read array cfi electronic signature status any state lock unlock lock-down bcr setup block lock unlock lock-down error, set bcr error block lock unlock lock-down error, set bcr error block lock unlock lock-down block block lock unlock lock-down error, set bcr error block lock unlock l ock- down error, set bcr error block lock unlock lock-down error, set bcr error block lock unlock lock-down error, set bcr error block lock unlock lock-down error, set bcr error block lock unlock lock-down block block lock unlock lock-down block set bcr error see modify tabl e read array read array read status register read array read elect. sign. read cfi block lock unlock lock-down setup, set bcr setup read array read array read array lock unlock lock-down block set bcr any state protection register done see modify tabl e read array read array read status register read array read elect. sign. read cfi block lock unlock lock-down setup, set bcr setup read array read array read array any state program- double/ quadruple program done see modify tabl e read array read array read status register read array read elect. sign. read cfi block lock unlock lock-down setup, set bcr setup read array read array read array setup program suspend read array, cfi, elect. sign., status see modify tabl e ps read array program (busy) ps read status register ps read array ps read elect. sign. ps read cfi ps read array ps read array ps read array ps read array idle erase suspend idle block/ bank erase setup erase error erase error erase (busy) erase error erase error erase error erase error erase error erase error erase error erase error any state error see modify tabl e read array read array read status register read array read elect. sign. read cfi block lock unlock lock-down setup, set bcr setup read array read array read array done setup erase suspend read array, cfi, elect. sign., status see modify tabl e es read array erase (busy) es read status register es read array es read elect. sign. es read cfi block lock unlock lock-down setup, set bcr setup es read array es read array es read array busy es read array idle erase (busy) program suspend es read array
m58cr032c, m58cr032d 62/63 table 37. command interface states - modify table note: ps = program suspend, es = erase suspend. current state of the other bank current state of the current bank command input to the current bank (and next state of the current bank) mode state others program setup (10h/40h) block erase setup (20h) program-erase suspend (b0h) protection register program setup (c0h) double/ quadruple program setup (30h/55h) bank erase setup (80h) setup read array, cfi, electronic signature, status register see lock tabl e read array read array read array read array read array read array busy idle program setup block erase setup protection register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array setup lock unlock lock-down bcr error, lock unlock lock-down block, set bcr see lock tabl e read array read array read array read array read array read array busy idle program setup block erase setup protection register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array idle protection register setup protection register (busy) protection register (busy) protection register (busy) protection register (busy) protection register (busy) protection register (busy) protection register (busy) setup busy busy done see lock tabl e read array read array read array read array read array read array idle program setup block erase setup protection register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array any state program double/ quadruple word program setup program (busy) program (busy) program (busy) program (busy) program (busy) program (busy) program (busy) idle busy ps read status register setup done see lock tabl e read array read array read array read array read array read array busy idle program setup block erase setup protection register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array setup program suspend read array, cfi, elect. sign., status register see lock tabl e ps read array ps read array ps read array ps read array ps read array ps read array idle erase suspend idle block/ bank erase setup see lock tabl e erase error erase error erase error erase error erase error erase error busy erase (busy) erase (busy) erase (busy) es read status register erase (busy) erase (busy) erase (busy) setup erase suspend read array, cfi, elect. sign., status register see lock tabl e es read array es read array es read array es read array es read array es read array busy idle program setup double/ quadruple program setup program suspend es read array es read array
63/63 m58cr032c, m58cr032d information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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